Elite Technical is seeking an experienced FPGA/DSP engineer for a long-term position in Palm Bay, FL. Due to the nature of the work to be performed, any candidate seeking to be considered must be a U.S. citizen with an active TS/SCI clearance.
This position will be responsible for providing FPGA DSP Design Engineering support to customer-funded programs and internal research efforts within our client's Intelligence, Surveillance and Reconnaissance (ISR) business unit.
Our client's ISR solutions serve a broad array of government, civil and commercial customers, particularly with respect to high-reliability airborne and space-based remote sensing payloads that offer active and motion imaging and data processing, exploitation and dissemination. The ISR business unit also provide solutions that map and monitor the earth for a variety of commercial and governmental users.
- Bachelor's Degree and minimum 9 years prior related experience or a Graduate Degree with a minimum of 7 years of prior related experience.
- Active TS/SCI Security Clearance
- Experience with the FPGA design process including requirements generation, preliminary design, peer reviews, detailed design, test plan generation, and integration and test.
- Ability to understand system requirements; capable of working with Systems Engineering to assist in the flow down the system requirements to the DSP FW/SW levels
- Solid understanding of signal processing concepts; ability to architect signal processing firmware and software; work closely with the engineering teams through design and implementation, integration, testing, and qualification of the deliverable system
- Experience with fixed-point digital math functions and implementations, floating point data structures, control theory (feedback systems and tracking), and communication theory
- Experience with Digital Signal Processing operations and optimization (FIR filters, Up/Down sampling, convolution, correlations-)
- Proficiency in MATLAB; able to implement algorithms in FPGAs from MATLAB code
- Utilize basic digital logic design concepts (understanding how VHDL code translates into logic primitives within an FPGA); understanding of all of the architectural elements within Xilinx or Altera FPGA
- Static timing analysis and the process by which timing closure is achieved in a design
- Experience with Cadence Incisive Enterprise Simulator; familiar with Subversion, Python, or Perl
- Work closely with the engineering teams through design, implementation, integration, testing, and qualification of the deliverable system
- Must be able to work independently and to lead a design team and negotiate solutions with Hardware / Software Engineering and Systems Engineering
- Experience with high speed memory interfaces.
- Experience with high speed serial protocols (PCI Express, SRIO, Ethernet).
- Experience with Analog to Digital (AD) and Digital to Analog (DA) interfaces.
- Experience with control protocols such AXI, I2C, SPI, RS-232/422, and SpaceWire.
- Experience managing flash file systems.
- Proficiency in MATLAB/Simulink DSP prototyping environments including DSP System Toolbox, Communications System Toolbox, etc.
- Proficiency managing source code in revision controls systems such as Subversion, ClearCase, GIT, etc.
- Experience with Xilinx Vivado and the ability to build FPGAs with difficult timing/routing constraints.
Palm Bay, FL
Monday, August 27, 2018
Wednesday, August 15, 2018
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