Verification ASIC/FPGA Engineer
100% Remote

Our client, a leading federal defense contractor is seeking a Verification ASIC FPGA Engineer responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments

Duties and Tasks:

- Determines architecture, system simulation and detailed design approach
- Defines module interfaces and all aspects of device design and simulation
- Creates test and simulation plans that establish functional criteria
- Verifies test results and analyzes performance
- May also review vendor capabilities and simulation tools
- Participates in the improvement of the ASIC/FPGA organizational processes
- Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle
- May provide leadership and/or direction to lower level employees
- Independently determines approach to solutions
- Contributes to the completion of major programs and projects
- Plans and executes project tasks for activities described above

Required Skills

- Due to the nature of work performed within our facilities, U.S. citizenship is required.
- Ability to obtain a DoD Secret clearance
- Bachelor-s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a
minimum of 3 years of relevant experience.
- In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
- In-depth knowledge of-System Verilog-object oriented-programming and the-Universal Verification Methodology (UVM)
- Understands-UVM Testbench-Architectures-
- Comfortable using and developing UVM-agents, bus functional-models
- Understands different types of-coverage, usage of cover classes, cover points, etc
- Experience with predictive testbench components,-functional coverage-and-assertions
- Experience with-constrained random-testing
- Experience with the-Register Abstraction Layer
- Familiarity with-requirements-based verification, requirement tracing, and developing requirement verification strategies etc
- Experience with scripting languages such as Linus-shell scripts, TCL, Python
- Familiarity with using-Formal-Verification tools, code coverage, writing waivers etc.
- Familiarity with the following are also helpful
- Questa Verification IP (QVIP)
- Developing UVM testbenches for designs implemented in-Xilinx-devices with Xilinx-IP-and-SoCs-
AXI-protocols, PCIe, Space Wire, and Ethernet interfaces-
- DSP-functions and common signal processing components
- Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
- Continuous Integration features of-GITLab