Senior Verification ASIC FPGA Engineer

Our client, a leading federal defense contractor has multiple openings for Senior Verification ASIC FPGA Engineer in their Scottsdale, AZ location. Once you join the team, you will be responsible for definition, design, verification and documentation for ASIC (Application Specific Integrated Circuit) and/or FPGA (Field Programmable Gate Array) developments.

This position is fully on-site Monday to Friday in Scottsdale, AZ.

Duties and Tasks:

- Determines architecture, system simulation and detailed design approach
- Defines module interfaces and all aspects of device design and simulation
- Creates test and simulation plans that establish functional criteria
- Verifies test results and analyzes performance
- May also review vendor capabilities, foundry technologies, device libraries and simulation tools
- Contributes to the generation and maintenance of work products (i.e. plans, specifications, design documentation, etc.) used for internal consumption and/or deliverable to external customers
- Develops and presents requirements, concepts, designs, decisions and results to internal management, other organizations, teammates and customers
- May contribute to technical subcontract management that may include SOW development, proposal evaluation, source selection, technical oversight, and subcontractor work product evaluation and acceptance
- Reviews vendor capability to support product development
- Applies a strong understanding of the organizationally defined processes throughout the lifecycle of the program or project
- Participates in the improvement of the ASIC/FPGA organizational processes
- Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the development life cycle
- Leads the research and analysis of data, such as customer design proposal, specifications, and manuals to determine feasibility of design or application
- Selects components and equipment based on analysis of specifications and reliability
- Contributes to the technical approach on small proposals
- Provides leadership and/or direction to lower level employees
- Leads technical tasks for small teams or projects
- Exercises latitude in determining technical objectives of assignments
- Guides the successful completion of major programs and projects

Required Skills

- Must be US Citizen due to government requirement
- Must be able to obtain a DoD Top Secret / SCI (active Secret or Top Secret is preferred).
- Bachelor-s degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 8 years of relevant experience; or Master's degree plus a
minimum of 6 years of relevant experience.

- 8+ years experience verifying FPGAs or ASICSs
- In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)
- Understands UVM Test bench Architectures
- Comfortable using and developing UVM agents, bus functional models
- Understands different types of coverage, usage of cover classes, cover points, etc.
- Experience with predictive test bench components, functional coverage and assertions
- Experience with constrained random testing
- Experience with the Register Abstraction Layer
- In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
- Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies etc
- Experience with scripting languages such as Linus shell scripts, TCL, Python
- Familiarity with using Formal Verification tools, code coverage, writing waivers etc.
- Familiarity with the following are also helpful
- Questa Verification IP (QVIP)
- Developing UVM test benches for designs implemented in Xilinx devices with Xilinx IP and SoCs
- AXI protocols, PCIe, Space Wire, and Ethernet interfaces
- DSP functions and common signal processing components
- Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration.
- Continuous Integration features of GITLab

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Location

Scottsdale, AZ

Openings

2

Anticipated Start Date

Saturday, February 24, 2024

Job Type

Contract

Anticipated Duration

12 months with option to extend/convert

Date Posted

Tuesday, January 28, 2025

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