Elite Technical is seeking experienced electrical engineers with a solid background in FPGA/ASIC design for a long-term direct hire position with a highly regarded client located in the waterfront area of Camden, New Jersey, just across the river from Philadelphia, PA.

The selected candidate will be part of the core design team, responsible for the architecture, implementation, verification/validation through software integration test, for delivery of complex FPGAs and/or ASICs systems. The selected candidate will develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL, HLS) with high speed protocols (NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration) targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) and/or ASICs.

Additionally, you will be responsible for writing/debugging tests/sequences for End-to-End simulation on a UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.

Our client has deployed state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA including HLS, Mentor Questa family, VIPs for UVM, Clock Domain Crossing (CDC), Catapult (HLS).

This is a key, high-impact, high-visibility role in the organization to ensure robust quality and delivery of communication products for National Security. Any candidate seeking consideration must be a U.S. citizen with a current/active secret security clearance.

Required Skills

The successful candidate will possess:
- Bachelor of Science in Electrical Engineering or Computer Science or equivalent
o Master of Science in Electrical Engineering or Computer Science preferred
- At least 6 years of experience with a proven track record of architecting, implementing high throughput digital cores / algorithms targeting Xilinx Zynq / MPSOC class FPGAs with interfaces Ethernet (UDP, TCP/IP), AXI, PCIe/NVMe, USB.
- Proficiency in VHDL, C++ (OOP) and System Verilog Assertions (SVA)
- Experience with debugging in ARM ecosystem with Linux OS
- Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)
- Excellent Analytical/Debug skills
- Good verbal, written, and presentation skills
- US citizenship with a minimum US Government Secret security clearance from the outset

Highly preferred:
Proficiency in High level synthesis (Xilinx Vivado HLS AND/OR Mentor Calypto) with C++.
Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS.
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